This invention relates to plasma doping method, and more particularly to an impurity doping method by irradiating the surface of a sample with plasma to dope the impurity into the sample.
In a silicon integrated circuit manufacturing process, processes of doping acceptor impurities such as boron, and donor impurities such as arsenic and phosphor are repeatedly necessary. For this purpose, it is general to transform impurities into ions, and to implant the ions by accelerating them in a range from tens of kV to several kV, but for doping into polycrystalline silicon to be used in a gate of a MOS transistor or the like, diffusion from phosphorus glass, arsenic glass or boron glass, etc. is generally employed. This is because the ion implantation is poor in throughput and too high in cost because the doping quantity into polycrystalline silicon is extremely large. The method of using phosphorus glass requires three steps of (1) deposition of glass, (2) heat treatment, and (3) removal of glass, and, moreover, since phosphorus glass deposits on an entire surface of a silicon substrate, it is hard to dope locally in a certain region. On the other hand, as gate material of CMOS LSI, n.sup.+ polycrystalline silicon has been conventionally used, but as channel length is shortened, it comes t be necessary to use n.sup.+ polycrystalline silicon at a n-channel side and p.sup.+ polycrystalline silicon at a p-channel side from the aspect of control of channel threshold voltage.
To fabricate n-type and p-type polysilicon gates into one chip, in prior art, ion implantation technique must be used. FIG. 1A is a diagram to explain formation of, for example, p-type polysilicon gate. On a polysilicon film 6 formed on a gate oxide film 4 on a silicon substrate 2, boron ions are implanted as indicated by arrow X with an energy of about tens of keV. In order to implant only into the p-type region, a resist 7a is selectively opened. Numeral 8 denotes a peripheral oxide film. In order to form an n-type polysilicon gate, ions of phosphor or arsenic are implanted into the polysilicon film 6.
This method is effective as far as the gate oxide film is thick and the polysilicon film is also thick, but it is no longer applicable the transistor size is reduced, the gate oxide film becomes thin, and the polysilicon film also becomes thin in the trend of higher density and higher performance. That is, in FIG. 1A, implanted ions penetrate through the gate oxide film 4 and, a layer 9 is formed beneath it. FIG. 2 is a diagram to show concentration distribution (simulation) from the boron surface when boron ions of 1.times.10.sup.16 /cm.sup.2 are implanted at an acceleration energy of 10 keV in the case of gate oxide film thickness of 13 nm and polysilicon film 6 thickness of 0.1 .mu.m above it. In an ordinary ion implantation of 10 keV, in spite of the lowest energy, it is known that boron has invaded up to the silicons substrate by penetrating through the gate oxide film 4. Such penetration of boron into the silicon substrate is not acceptable because the threshold voltage of the MOS transistor is varied. Besides, as shown in FIG. 1B, generally in forming source and drain electrode region 10, it is necessary to dope the impurities of high concentration locally respectively by dividing into the p-type region and n-type region, and it is forced to use an expensive ion implantation machine. However, in the source and drain electrodes, too, smaller depth of junction x.sub.j is required as transistor size is reduced. As described previously, especially in p-channel MOS, since boron ions of relatively light weight are used, the depth of junction reaches as much as 0.3 .mu.m as shown in FIG. 2 earlier even if implanted at the lowest energy of 10 keV in the existing ion implantation machine. To solve this problem, molecule ions such as BF.sup.+.sub.2 ions are used, but fluorine impurity forms defects at interface between silicon and oxide film, metal silicide film, etc.
It hence gives rise to necessity of a method of doping locally and at low cost.
As a method which satisfies such need, a plasma doping device is known (disclose, for example, in Monthly Semiconductor World, p. 158, 1882, Vol. 2, in Japanese). A conventional plasma doping device is explained by referring to FIG. 3. Inside a grounded vacuum chamber 14, a gas containing doping impurities, such as diborane (B.sub.2 H.sub.6) and arsine (AsH.sub.3), is introduced through a gas inlet 16, and is discharged from an exhaust port 18 by a vacuum exhaust device (not shown), so that the internal pressure is kept between one to several Torr. A metallic sample table 20 placed in the chamber 14 is connected to a DC power source 22, and a silicon substrate (wafer) 2A is put in the sample table 20. When a DC voltage of several hundred volts is applied to the sample table 20 through DC power source 22, the gas in the chamber 14 is transformed into plasma by glow discharge, and the impurity ions to be doped are accelerated by the electric field in an ion sheath 26 formed around the sample table 20 and wafer 2A working as the cathodes, and are doped into the wafer 2A. Generally, the wafer 2A is heated to 200.degree. to 300.degree. C. because it is directly exposed to plasma, but at the degree of vacuum in the DC or RF discharge region (10.sup.-2 Torr or less), if the substrate is at low temperature, such as about 200.degree. C., a thin film of the impurities to be doped is deposited on the wafer surface, and hence the substrate is further heated by a heater 28 embedded in the sample table 20.
Such device is partly applied in the silicon integrated circuit manufacturing process when doping impurities at high concentration from contact holes in order to reduce the contact resistance between the aluminum electrode and silicon diffusion layer after contact hole forming process.
When doping impurities by using a material withstanding high temperature of oxide film such as a contact hole as mask, such conventional plasma doping device is effective because it is possible to dope locally at low cost, but when it was necessary to use a photoresist as mask, the wafer temperature became too high and it was not appropriate. For example, when using both p.sup.+ polycrystalline silicon and n.sup.+ polycrystalline silicon as the gate material for enhancing the performance of CMOS LSI, only the regions to dope are opened by using a resist in order to keep the number of process at minimum, and p-type impurity and n-type impurity are injected into the non-dope polycrystalline silicon at a high concentration of over 10.sup.16 /cm.sup.2, but in the conventional plasma doping device, since the operation exceeds the heat resistance limit (about 200.degree. C.) of the photoresist, it was forced to use an expensive ion implantation device for a long time.
Incidentally, in a vacuum range of 7.5.times.10.sup.31 4 to 7.5.times.10.sup.31 1 Torr, a method of generating plasma at high density despite high degree of vacuum by applying a magnetic field in the direction along the surface of substrate is known (Japanese Laid-Open Pat. No. 6126219). In this method, however, since the closest part of the substrate is exposed to plasma of highest density, the substrate temperature is elevated in an extremely short time, instantly exceeding the heat resistance limit of the resist. Although it is possible to dope in this short time, it is hard to control the concentration of the impurity to be doped. That is, since start of discharge is often unstable, it is better to take enough time in order to achieve high reproducibility of concentration control. Besides, since the plasma density is a high concentration, if it is attempted to form a doped layer of a properly low concentration, the doping time must be shortened extremely, for example, within 1 second. As its countermeasure, it is necessary to dilute the material gas (e.g. B.sub.2 H.sub.6, PH.sub.3, AsH.sub.3) with base gas (He, H.sub.2, etc.), and dope in a sufficient time, and hence it is difficult to dope at high reproducibility and excellent concentration control, while keeping above the heat resistance limit of the resist.
In the explanation about this method, meanwhile, nothing is mentioned about the process of using the resist as the mask.